# MXEN3004/ETEN6000 Design Assignment

MXEN3004/ETEN6000 Design Assignment

Control problem

From the step response of an industrial plant, identify a first-order plus dead time model

µ -Ls

G e .

Then, using the model G(s), design a feedback compensator that satisfies the following criteria

1. gain crossover frequency ;

2. phase margin fm = 60o;

3. given a step reference signal, the tracking error is zero;

4. given a ramp reference signal with slope R, the tracking error satisfies er 3t R;

5. the closed-loop system attenuates of at least a measurement noise at frequencies .

1 Identification

Use Matlab and the file systems generator.p obtain the unit step response of the plant as

[y,t]=systems generator(N)

where N is your student number. Please ensure that you use the correct student number. From the step response identify the parameters µ, L and t. (hint: find µ imposing the dc-gain, then find L as the time when the response of the real systems reaches 20% of the steady-state and finally find t imposing that the response of G(s) matches the one of the plant at 63% of the steady state; see also Example 4 of “delay and higher order.pdf” from Lecture 4). Verify your model by plotting on the same figure the step response obtained from systems generator and the unit step response of G(s).

2 Integral controller

Using G(s) with the parameters identified in the previous step, design a controller

k

C(s)=

s

that satisfies condition 1). (Hint: find k imposing that Show that condition 2) is not satisfied.

Show that the conditions 3) and 4) are satisfied.

3 PI controller

Using G(s) with the parameters identified in the first step, design a controller

k(t1s+1)

C(s)=

s

that satisfies conditions 1) and 2). (Hint: find t1 such that condition 2 is satisfied, and then find k imposing that . Always impose conditions with some margin, for example, impose a phase margin larger than the bare minimum of 60?.) Verify that conditions 3) and 4) are satisfied. Show that condition 5 is not satisfied.

4 Filtered PI controller

Using G(s) with the parameters identified in the first step, design a controller

k(t1s+1) C(s)=

(t2s+1)s

that satisfies all conditions. (Hint: use t1 from the previous step, obtained with a sufficiently large phase margin, find t2 such that condition 5 is satisfied, and then find k imposing that . Show that all conditions are satisfied.

To verify your final design, using the transfer function G(s) obtained identified in step 1

• plot the closed-loop unit step response;

• plot the error in response to a unit ramp input;

• plot the closed-loop response to a sinusoid with angular frequency ?c;

• show the Bode (or margin) plot of the loop-gain transfer function L(s) to show that the required crossover frequency and phase margin have been achieved;

• verify that the magnitude of the frequency response of the closed-loop transfer function at 100 is less than 0.001.

If any of the design criteria cannot be achieved, then get as close as you can and explain where compromises were required.

This is a controller design assignment, and should be documented as such. The use of MATLAB for relevant calculations and plots is encouraged. Plots and calculations should be explained in the context of the design task and the required performance of the closed loop system. A brief introduction and conclusion should be included, but do not use the text of the assignment document directly in your submission.

Please ensure that a clear statement of your student Name and student ID is made in the front page. Your report should be limited to a maximum of 5 pages, including graphs and parts of code that contains relevant calculations. Do not include all your code. Include only the relevant lines of code, where (and if) you think it is appropriate in the context of you report. You can have extra pages exclusively for title, table of contents and bibliography, if any. No other content (e.g., appendices) is allowed in the extra pages.

Anything in the body of the report that goes beyond the five pages will not be marked.

If the design is carried out using a response obtained with the wrong student number, the final mark is reduce by 50%

The report is due in Turnitin by 11:59pm, Sunday May 23rd, 2021.